Solid State Technology and Devices Seminar: EUV Lithography: the Road to HVM and Beyond

Seminar: Solid State Technology and Devices | October 19 | 1-2 p.m. | Cory Hall, 521 Hogan Room

 Dr. Anthony Yen, ASML Lithography

 Electrical Engineering and Computer Sciences (EECS)

Development of EUV lithography for high-volume manufacturing started in early 2000s. In 2018, 250W of source power became available in the field, giving EUV exposure systems a throughput of >140 wph at an exposure dose of 20 mJ/cm2. Concurrently, the rate of power degradation due to collector contamination has been driven down so that high system throughput can be maintained. Based on this and progress made in other areas of the technology infrastructure, EUV will enter HVM in 2019 to provide the necessary technology for continued economical scaling of integrated circuits. ASML continues to improve the performance of EUV systems with higher throughput and tighter overlay specifications to further enhance their productivity and capability. At the same time, our phase-inclusive source-mask optimization technique maximizes the lithographic process latitude. For manufacturing with EUV lithography beyond the first generation, issues such as the stochastic behavior of photoresists and the three-dimensional nature of the photomask are being addressed to enable single patterning at lower k_1 values. Overcoming these limitations will allow EUV lithography to extend into the next decade with minimal use of double patterning. Finally, ASML has started to develop the next-generation NA=0.55 EUV exposure tools to enable scaling in semiconductor manufacturing well into the next decade.

 CA,, 5106423214