Dissertation Talk: Configurable Data Converters for Digitally Adaptive Radio
Presentation: Dissertation Talk: EE | August 17 | 2-3 p.m. | 2108 Allston Way (Berkeley Wireless Research Center), Rabaey Room
Amy Whitcombe, UC Berkeley
As wireless connectivity has evolved into an essential component of daily life, modern wireless systems must satisfy exponentially growing demand for data in an energy- and cost-efficient manner. New techniques such as digital beamforming can support multiple users with many-element radio arrays, but the required performance of each radio element varies with array size. Additionally, while conventional single-element radios are typically designed to meet stringent performance requirements outlined in wireless standards, peak performance is rarely required. Adaptive radios that configure performance to suit system-level needs may therefore serve as building blocks for energy-efficient wireless platforms, leveraging enhanced digital processing capabilities afforded by CMOS technology scaling to realize fully integrated smart wireless systems. However, high-performance analog circuits such as wireless receivers are often difficult to build in advanced process nodes optimized for digital performance. To that end, this talk will discuss circuit-level and architectural approaches to building analog-to-digital interface circuits for receivers that are both configurable to enable adaptation and well-suited to implementation in scaled CMOS nodes.
First, the talk will discuss the development of a resolution-scalable successive approximation (SAR) analog-to-digital converter (ADC) in a 65nm process that can be used as a building block for variable-element digital beamforming arrays. Second, this talk will describe a reconfigurable, digital-intensive RF-to-digital converter architecture that uses a SAR ADC with integrated discrete-time filtering to provide high linearity and a voltage-controlled oscillator (VCO) based ADC to improve sensitivity. By replacing the high-performance active amplifiers and filters used in conventional receivers with an ADC constructed from digital building blocks, the 16nm FinFET prototype is highly process-scalable. Overall, the techniques proposed in this talk present a path towards utilizing the advantages of CMOS scaling to create digitally adaptive wireless systems.