Dissertation Talk: Negative Capacitance Transistors: Numerical Simulation, Compact Modeling and Circuit Evaluation

Presentation | December 11 | 4-5 p.m. | 521 Cory Hall

 Juan Pablo Duarte, UC Berkeley

 Electrical Engineering and Computer Sciences (EECS)

Negative capacitance FETs (NC-FETs) are quickly emerging as preferred candidates for extremely scaled technologies for digital and analog applications. The recent discovery of ferroelectric (FE) materials using conventional CMOS fabrication technology has lead to the first demonstrations of FE based NC-FETs. The ferroelectric material layer added over the transistor gate insulator help in several device aspects, it suppress short-channel effects, increase on-current due voltage amplification, increase output resistance in short-channel devices, etc. These exciting characteristics has created an urgency for analysis and understanding of device operation and circuit performance, where numerical simulation and compact models are playing a key role.

This talk will give insights into the device physics and behavior of FE based negative capacitance FinFETs (NC-FinFETs) by presenting numerical simulations, compact models, and circuit evaluation of these devices. NC-FinFETs may have a floating metal between FE and the dielectric layers, where a lumped charge model represents such a device. For a NC-FinFET without a floating metal, the distributed charge model should be used, and at each point in the channel the FE layer will impact the local channel charge. This distributed effect has important implications on device characteristics. These device differences are explained using numerical simulation and correctly captured by the proposed compact models. The presented compact models have been implemented in comercial circuit simulators for exploring circuits based on NC-FinFET technology. Circuit simulations show that a quasi-adiabatic mechanism of the ferroelectric layer in the NC-FinFET recovers part of the energy during the switching process of transistors, helping minimizing the energy losses of the wasteful energy dissipation nature of conventional transistor circuits. As circuit load capacitances further increase, VDD scaling becomes more dominant on energy reduction of NC-FinFET based circuits.