Lifetime Simulation of Semiconductor Circuits

Seminar | October 5 | 3-4 p.m. | 529 Cory Hall

 Linda Milor, Professor, Georgia Institute of Technology

 Electrical Engineering and Computer Sciences (EECS)

Technology scaling has resulted in higher operating temperatures and electrical fields, and this has contributed to faster device and interconnect aging. As a result, wearout has become a more important problem.

Technology qualification and monitoring for reliability involves checking the lifetime of test structures, together with area scaling and scaling to use conditions, to project the lifetime of a full chip from that of a test structure, tested under accelerated conditions. These methods to link the lifetime of a test structure to a circuit do not take into account the details of operation. Our work aims to include operating details in lifetime estimates. We consider a wide variety of wearout mechanisms, including bias temperature instability, hot carrier injection, gate oxide breakdown, backend dielectric breakdown, electromigration, and stress-induced voiding. For wearout mechanisms associated with sudden and hard breakdown, we link process-level lifetime models of layout features to operating conditions (determined by system emulation with benchmarks). The feature-level lifetime models are combined to estimate system lifetime (with and without redundancy). For wearout mechanisms associated with gradual degradation, we determine the statistical distribution of the time when circuit performances fail, taking into account the performance requirements and operating conditions.

Speaker biography: Dr. Milor has worked in the fields of yield analysis, reliability, and testing since the mid-1980s. She has over 150 publications in these areas. She has a Ph.D. from U.C. Berkeley in Electrical Engineering. She is currently a Professor of Electrical and Computer Engineering at Georgia Tech. She has worked both in academia and industry. In academia she received the prestigious NSF Career Award and the 2004 Best Paper in the IEEE Transactions on Semiconductor Manufacturing for M. Orshansky, L. Milor, and C. Hu, "Characterization of Spatial Intra-Field Gate CD Variability, Its Impact on Circuit Performance, and Spatial Mask-Level Correction", published in Feb. 2004. She received a best paper award from the International Conference on Computer Design in 2009 for F. Ahmed and L. Milor, "Reliable Cache Design with Detection of Gate Oxide Breakdown Using BIST". She received the best interactive presentation award from Design Automation and Test in Europe for M. Bashir and L. Milor, "Towards a Chip Level Reliability Simulator for Copper/Low-K Backend Processes". She received the best paper award from the European Symposium on Reliability of Electron Devices, Failure Physics and Analysis for "System-Level Variation-Aware Aging Simulator Using a Unified Novel Gate-Delay Model for Bias Temperature Instability, Hot Carrier Injection, and Gate Oxide Breakdown". In industry, she worked as a Product Engineering Manager at Advanced Micro Devices, where she was responsible for yield and wafer quality.

 linda.milor@ece.gatech.edu