On-chip active delay lines with widely tunable delays

Seminar | April 6 | 10:30-11:30 a.m. | 540 Cory Hall

 Nagendra Krishnapura, Indian Institute of Technology, Madras

 Electrical Engineering and Computer Sciences (EECS)

An all-pass filter architecture that can be generalized to high orders, and can be realized using active circuits, is proposed. Using this, a compact true-time-delay element with a widely tunable delay and a large delay-bandwidth product is demonstrated. This is useful for beamforming and equalization in the lower GHz range where the use of LC or transmission line based solutions to realize large delays is infeasible. Coarse tuning of delay is realized by changing the filter’s order while keeping the bandwidth constant and fine tuning is implemented by changing the filter’s bandwidth utilizing the delay-bandwidth tradeoff. A test chip fabricated in 130nm CMOS process demonstrates a delay tuning range of 0.25 to 1.7ns over a bandwidth of 2GHz, while maintaining a magnitude deviation of +/-0.7 dB. The filter has a worst case noise figure of 23dB, and -40dB IM3 distortion for 37 mV ppd inputs. The chip dissipates 112 to 364 mW of power between its minimum and maximum delay settings. Computed radiation pattern with four antennas spaced λ(fmax)/2 apart shows +/-90 degree beam steering off broadside. The filter's delay-bandwidth product of 3.4, which, combined with a small active area of 0.6mm^2, corresponds to a substantial improvement over the state-of-the-art of on-chip
active delay lines.

In addition to the above, I will briefly describe some of the other work done in our group.

 jr@berkeley.edu