UC Berkeley Events Calendar
http://events.berkeley.edu/index.php/calendar/sn/pubaff.html
Campus-wide event listings from the University of California, BerkeleyHow to Write a Research Proposal Workshop, Dec 11
http://events.berkeley.edu/index.php/calendar/sn/pubaff.html?event_ID=112986&date=2017-12-11
If you need to write a grant proposal, this workshop is for you! You'll get a headstart on defining your research question, developing a literature review and a project plan, presenting your qualifications, and creating a realistic budget. <br />
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The workshop is open to all UC-Berkeley students (undergraduate, graduate, and visiting scholars) regardless of academic discipline. It will be especially useful for upper-division undergraduates preparing to write a senior honors thesis, as well as those applying for graduate school or considering a career in fundraising for nonprofits. <br />
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We strongly recommend that you come to the workshop with a specific topic in mind. Your idea can be broad--we'll refine it during the workshop--but you'll get the most out of the workshop will be most useful if you can apply it to a specific area of research interest.http://events.berkeley.edu/index.php/calendar/sn/pubaff.html?event_ID=112986&date=2017-12-11Arithmetic Geometry and Number Theory RTG Seminar, Dec 11
http://events.berkeley.edu/index.php/calendar/sn/pubaff.html?event_ID=113707&date=2017-12-11
Michael Artin and Barry Mazur's classical comparison theorem tells us that for a pointed connected finite type $\mathbb C$-scheme $X$, there is a map from the singular complex associated to the underlying topological spaces of the analytification of $X$ to the étale homotopy type of $X$, and it induces an isomorphism on profinite completions. I'll begin with a brief review on Artin-Mazur's étale homotopy theory of schemes, and explain how I extended it to algebraic stacks under model category theory. Finally, I'll provide a formal proof of the comparison theorem for algebraic stacks using a new characterization of profinite completions.http://events.berkeley.edu/index.php/calendar/sn/pubaff.html?event_ID=113707&date=2017-12-11Dissertation Talk: Negative Capacitance Transistors: Numerical Simulation, Compact Modeling and Circuit Evaluation, Dec 11
http://events.berkeley.edu/index.php/calendar/sn/pubaff.html?event_ID=113617&date=2017-12-11
Negative capacitance FETs (NC-FETs) are quickly emerging as preferred candidates for extremely scaled technologies for digital and analog applications. The recent discovery of ferroelectric (FE) materials using conventional CMOS fabrication technology has lead to the first demonstrations of FE based NC-FETs. The ferroelectric material layer added over the transistor gate insulator help in several device aspects, it suppress short-channel effects, increase on-current due voltage amplification, increase output resistance in short-channel devices, etc. These exciting characteristics has created an urgency for analysis and understanding of device operation and circuit performance, where numerical simulation and compact models are playing a key role.<br />
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This talk will give insights into the device physics and behavior of FE based negative capacitance FinFETs (NC-FinFETs) by presenting numerical simulations, compact models, and circuit evaluation of these devices. NC-FinFETs may have a floating metal between FE and the dielectric layers, where a lumped charge model represents such a device. For a NC-FinFET without a floating metal, the distributed charge model should be used, and at each point in the channel the FE layer will impact the local channel charge. This distributed effect has important implications on device characteristics. These device differences are explained using numerical simulation and correctly captured by the proposed compact models. The presented compact models have been implemented in comercial circuit simulators for exploring circuits based on NC-FinFET technology. Circuit simulations show that a quasi-adiabatic mechanism of the ferroelectric layer in the NC-FinFET recovers part of the energy during the switching process of transistors, helping minimizing the energy losses of the wasteful energy dissipation nature of conventional transistor circuits. As circuit load capacitances further increase, VDD scaling becomes more dominant on energy reduction of NC-FinFET based circuits.http://events.berkeley.edu/index.php/calendar/sn/pubaff.html?event_ID=113617&date=2017-12-11