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DTSTAMP:20120213T224014Z
DTSTART;TZID=America/Los_Angeles:20120406T130000
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TRANSP:OPAQUE
SUMMARY:SOI-Enabled Technologies for 3D Circuit Integration and Ultra Low Power Applications
UID:52715-ucb-events-calendar@berkeley.edu
ORGANIZER;CN="UC Berkeley Calendar Network":
LOCATION:521 Cory (Hogan Room) Cory Hall
DESCRIPTION:Dr. Steven A. Vitale\, MIT Lincoln Laboratory\, Lexington\, MA\n\nThe Microelectronics Laboratory (MEL) at MIT Lincoln Laboratory (MIT/LL) is\nthe leading semiconductor research and advanced prototyping facility\ndedicated to supporting the current and future needs of the Department of\nDefense. The MEL also supports microelectronics research for non-DoD\nagencies including NASA and national laboratories\, and fabricates circuits\nusing novel device technologies free-of-charge to university contributors\nthrough government-sponsored multiproject wafer runs. This presentation will\nexplore two of the novel silicon technologies developed at and made\navailable through MIT/LL: complex 3-dimensional (3D) circuit integration and\nan optimized ultra-low-power 0.3V CMOS process technology. \n\nAn overview of the factors driving the development of 3D circuit integration\ntechnologies and the variety of 3D integration approaches currently being\nexplored throughout the semiconductor industry will be provided. MIT Lincoln\nLaboratory has developed and demonstrated a unique 3D integrated circuit\ntechnology enabling monolithic integration of multiple transistor tiers on\none chip\, prior to packaging. This integration takes advantage of the thin\nsilicon body and buried oxide layer present in SOI devices to interconnect\nindependently-fabricated tiers of SOI transistors to create multiple-tier\ncircuits with the world's highest-density of 3D vias and smallest 3D-via\npitch. The technology allows extremely low capacitance and resistance per\ninterconnection\, integration of different process technologies\, integration\nof mixed materials (e.g.\, Si and III-V)\, and it is extendable to any number\nof layers. Some examples of completed 3D circuits including the world's\nfirst 3-tier SRAM\, advanced focal planes\, a 3D FPGA\, and a bio lab-on-a-chip\nrealized in this technology will be discussed.\n\nThe second part of presentation will discuss an ultra-low-power transistor\ntechnology which can expand the technological capability of handheld and\nwireless devices by dramatically improving battery life and portability.\nUbiquitous sensor networks\, RFID tags\, implanted medical devices\, portable\nbiosensors\, handheld devices\, and space-based applications are among those\nwhich benefit from extremely low power circuits. For these systems\, by\noperating an optimized SOI low-capacitance transistor at 0.3 V\, below the\nthreshold voltage of the device\, a 97% reduction in switching energy can be\nachieved compared to conventional transistors. By developing a fabrication\nprocess from the substrate material through the interconnect metal\,\noptimized for subthreshold transistor performance\, a device is realized with\nthe minimum switching energy and off-state current without significant\nimpact to the energy-delay product. The fully-depleted SOI mid-gap metal\ngate process technology will be discussed in detail\, as well as device and\ntest circuit results\, and multiproject wafer run opportunities for\ncollaborators.
URL:http://events.berkeley.edu/index.php/calendar/sn/pubaff.html?event_ID=52715&view=preview
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CREATED:20120213T224014Z
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