Dissertation Talk: Unlocking Design Reuse with Hardware Compiler Frameworks

Presentation | August 21 | 10-11 a.m. | 380 Soda Hall

 Electrical Engineering and Computer Sciences (EECS)

Emerging applications from the edge to the cloud are constantly increasing demand for energy efficient and performant computation. While specialized hardware can meet these power and performance goals, the high non-reoccurring engineering (NRE) costs of designing, testing, and verifying custom hardware severely hinders its supply. Hardware construction languages such as Chisel enables hardware designers to write parameterized hardware libraries which increase design reuse by turning NRE effort into reusable solutions for future specialized chips. This talk introduces Chisel’s hardware compiler framework, FIRRTL, which additionally enables automatic and custom RTL-transformations including logic optimization and instrumentation. By also introducing an aspect-oriented programming model to Chisel, this talk demonstrates reusable solutions for other large NRE costs including design verification and physical design floorplanning.

 Students - Graduate

 All Audiences

 adamiz@eecs.berkeley.edu