Dissertation Talk: Design Techniques for Energy-Efficient, Low Latency High-Speed Wireline Links
Presentation: Dissertation Talk: EE | May 16 | 8-9 a.m. | 2108 Allston Way (Berkeley Wireless Research Center), Rabaey Room
As data and computing systems get larger with more elements composing a single system, streamlined computation and data communication has put an ever-increasing demand on throughput of high speed SerDes. Industrial standards have responded to this trend by increasing the data-rate of chip I/Os, demanding doubling per-pin data-rate around every four years while the power budget remains the same. To address the challenge of per-pin bandwidth, receive side techniques, including an integrating CTLE, FFE and DFE, are demonstrated in a 60Gb/s non-return-to-zero transceiver with adaptive equalization achieving 60Gb/s with >0.3 UI opening at 10-12 Bit Error Rate (BER), while consuming 288 mW and occupying 2.48 mm2.
Furthermore, supporting this throughput in multi-chip module, distributed systems as seen in stacked 3-D and 2.5-D GPU-memory machine-learning driven systems calls for links, which are able to quickly turn on and off and operate efficiently in low utilization modes while supporting capability for maximum throughput. This talk presents a 2-tap switch-capacitor transmitter with FFE equalization that allows for a fully dynamic architecture operating at a nominal data-rate of 20Gb/s while maintaining energy-efficiency during both high and low link utilization. Additionally, a rapid-on/off voltage controlled LC oscillator uses resonant clocking to save power by directly driving the data-path capacitive loads all while improving overall latency, and a phase interpolator with a phase adjustable clock divider allows for the lowest achievable latency design for a 64:1 1-latch serializer implementation. The transmitter was taped out in TSMCs 28nm GP process achieving 1.2ns startup time and 0.72-0.62 pJ/bit at 1-20Gb/s while occupying 0.19mm2.