Dissertation Talk: FPGA-Accelerated Evaluation and Verification of RTL Designs
Presentation: Dissertation Talk: CS | May 6 | 9:30-10:30 a.m. | 380 Soda Hall
Cycle-level microarchitectural software simulation is the bottleneck of the hardware/software co-design flow due to its slow speed and the difficulty of simulator validation. Abstract power/energy models are only accurate for designs closely matching the template for which the model was constructed and validated. Moreover, the increasing complexity of modern hardware design makes verification challenging, and verification often dominates design costs.
This thesis describes fast and accurate RTL simulation methodologies for performance, power, and energy evaluation as well as verification and debugging using FPGAs in the hardware/software co-design flow. First, I will present MIDAS v1.0 that automatically generates FPGA-accelerated performance simulators from any RTL designs. Next, I will demonstrate DESSERT as an effective methodology for RTL debugging by running two identical deterministic simulators on FPGAs to detect and replay errors. For power and energy modeling, I will show i) Strober, a sample-based energy modeling, which takes random samples from long-running applications and replay them on RTL/gate-level simulation for average power estimation, and ii) Simmani, an activity-based power modeling, which automatically identifies key signals for dynamic power dissipation to construct runtime power models for any RTL designs.