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TALK: Dr. Antonino Tumeo - PNNL: Designing Next Generation Massively Multithreaded Architectures for Irregular Applications

Lecture: Departmental | December 10 | 2-3:30 p.m. | Soda Hall, 380 Soda, 3rd floor

Dr. Antonino Tumeo, Pacific Northwestern National Laboratory

Parallel Computing Laboratory

TALK: Dr. Antonino Tumeo - PNNL, Mon, Dec 10 at 2pm in 380 Soda Hall

Speaker: Dr. Antonino Tumeo - Pacific Northwest National Laboratory

Title: Designing Next Generation Massively Multithreaded Architectures for Irregular Applications

Abstract: Irregular applications, such as data mining or graph-based computations, show unpredictable memory/network access patterns and control structures. Massively multi-threaded architectures with large node count, like the Cray XMT, have been shown to address their requirements better than commodity clusters. In this talk we present the approaches that we are currently pursuing to design future generations of these architectures. First, we introduce the Cray XMT and compare it to other multithreaded architectures. We then propose an evolution of the architecture, integrating multiple cores per node and next generation network interconnect. We advocate the use of hardware support for remote memory reference aggregation to optimize network utilization. For this evaluation we developed a highly parallel, custom simulation infrastructure for multi-threaded systems. Our simulator executes unmodified XMT binaries with very large datasets, capturing effects due to contention and hot-spotting, while predicting execution times with greater than 90% accuracy. We also discuss the FPGA prototyping approach that we are employing to study efficient support for irregular applications in next generation manycore processors.

Bio: Dr. Antonino Tumeo received the M.S degree in Informatic Engineering, in 2005, and the Ph.D degree in Computer Engineering, in 2009, from Politecnico di Milano in Italy. Since February 2011, he has been a research scientist in the PNNL's High Peformance Computing group. He Joined PNNL in 2009 as a post doctoral research associate. Previously, he was a post doctoral researcher at Politecnico di Milano. His research interests are modeling and simulation of high performance architectures, hardware-software codesign, FPGA prototyping and GPGPU computing.