Skip to main content.
Advanced search >
<< Back to previous page Print

<< Thursday, November 15, 2012 >>

Remind me

Tell a friend

Add to my Google calendar (bCal)

Download to my calendar

Bookmark and ShareShare

Dissertation Talk: Design of Multi-Gb/s Multi-Coefficient Mixed-Signal Equalizers

Seminar | November 15 | 3:30-4:30 p.m. | 2108 Allston Way (Berkeley Wireless Research Center), BWRC Classroom

Chintan S Thakkar, EECS, UC Berkeley

Electrical Engineering and Computer Sciences (EECS)

The explosion of personal devices that need ubiquitous connectivity is making both wireless and wireline communication experience increasingly rapid growth in data-rates. Wireless channels have been ‘fortunate’ to see new channels/standards being made available over the past decade to meet up to multi-Gb/s demands – one such medium being the wideband 60GHz channel.

Wireless mediums, by definition however, are thwarted by multi-path reflection-based inter-symbol interference (ISI) – a problem which only gets becomes worse at higher speeds. For decades, equalizers have been used efficiently to mitigate such interference. However, wireless equalizers in commercial CMOS products are typically implemented in DSP using multi-level modulation schemes like OFDM, which when scaled to Gb/s speeds dissipate multi-Watt power. This is particularly detrimental for handheld/mobile devices with limited battery capacity.

To ease the power bottleneck for equalization, this work instead proposes using mixed-signal techniques. As opposed to classic multi-level ADC/DSP design, such techniques are inspired by high-speed chip-to-chip wired communication that advocates use of simple modulation schemes (such as QPSK) with few comparators. Since wireless channels suffer ISI with longer delay spreads than wired counterparts, previously developed wireline equalizers cannot be directly ported. This work therefore enables energy-efficient equalizers to cancel extremely long ISI delay spreads. Our first prototype demonstrated a 40-coefficient complex (I/Q) decision feedback equalizer (DFE) in 65nm CMOS to enable 10Gb/s rates over line-of-sight (LOS) 60GHz channels, while consuming only 14mW of power. The second prototype in 65nm low-power (LP) CMOS enables non-line-of-sight (NLOS) channel equalization as well, by using a 32-coefficient receiver feedforward equalizer (FFE) and a longer 100-coefficient DFE, achieving 3.5-8Gb/s rates while consuming 20-67mW.

While the equalizer prototypes have been targeted towards 60GHz channels, the techniques enable energy-efficient equalization for long ISI delay spreads for any high-speed communication link., 510-2201075