Par Lab Seminar: Rigel: A 1000+ Core Substrate for High-Throughput Computing

Seminar: Par Lab | November 12 | 11 a.m.-12:30 p.m. | Soda Hall, 430-438 (Wozniak Lounge)

Speaker/Performer: Sanjay J. Patel, University of Illinois at Urbana-Champaign

Sponsor: Par Lab

Chip architectures such as Nvidia G80 initiated the era of massively parallel general purpose computing on the client. Fueling the economic fire for such high-performance chips are interactive, client application domains such as gaming that are hungry for performance. Emerging applications in vision, imaging, video processing, virtual immersion, and robotics also have an insatiable need for speed, and provide a future performance roadmap for such many-core chips.

In the Rigel Project, we are developing a scalable architecture with 1000s of cores, and many TFLOPS of peak performance. Rigel has a well-defined and general-purpose programmer interface that enables a broad class of task and data parallel applications to be mapped efficiently to the chip. In this talk I will describe the major results of the project thus far, touching on subjects such as scalable cache coherence through hardware and software, the Rigel task-based parallel programming model, area-power-performance tradeoffs for throughput-oriented architectures, and parallel programming tools.

Event Contact: lrebusi@eecs.berkeley.edu, 510-643-1455