CANCELLED - [Dissertation Talk] Oxygen-insertion Technology for CMOS Performance Enhancement

Colloquium: Dissertation Talk: EE | October 9 | 2-3 p.m. | Cory Hall, 400 (Hughes Room) | Canceled

 Xi(Robin) Zhang, EECS Department

 Electrical Engineering and Computer Sciences (EECS)

Until 2003, the semiconductor industry followed Dennard scaling rules to improve transistor performance. However, due to gate-leakage-limited gate-oxide thickness scaling, short-channel effects have limited performance gains with further reductions in transistor gate length. Reductions in source/drain contact area result in increased parasitic resistance, which also limits circuit performance gains. This talk will describe the benefits of “oxygen insertion” (OI) technology to mitigate these issues for transistor scaling toward atomic dimensions.

Firstly, OI technology will be introduced, and its benefits for formation of ultra-shallow junctions (USJs) relevant for deep-sub-micron planar CMOS transistors will be presented. Experimental results show that OI technology can mitigate the increase in sheet resistance with decreasing junction depth, due to enhanced dopant retention during post-implantation thermal annealing. Next, the benefit of OI technology for forming a super-steep retrograde (SSR) channel doping profile in fin-shaped transistors (FinFETs) is discussed. Three-dimensional device simulations show that SSR FinFET technology is superior to silicon-on-insulator (SOI) FinFET technology for low-power static memory (SRAM) application. Finally, the potential benefit of OI technology for reducing the specific contact resistivity for a p-type silicon contact is discussed. Physical, chemical and electrical characterization results show that OI technology can provide for lower Schottky barrier height to mitigate the contact resistance issue exacerbated by transistor miniaturization.

Advisor: Tsu-Jae King Liu

 xi.zhang@berkeley.edu, 510-6938436