Dissertation Talk: BAG - Automation Framework for AMS Circuit Generator Design
Presentation: Dissertation Talk: Berkeley Wireless Research Center (BWRC): EE | December 5 | 3-4 p.m. | 2108 Allston Way (Berkeley Wireless Research Center), Rabaey room
Eric Chang, UC Berkeley
As the nature of scaling has shifted due to both technological and economic barriers, innovations in systems and circuits have become increasingly necessary to meet the needs to next generation designs. However, the stringent and unintuitive design rules of advanced multi-patterned processes along with increased interconnect resistance and capacitance due to dimensional scaling severely lengthen the time spent in post-layout verification and limit designers' ability to explore new circuit designs.
To significantly improve designers' productivity, we advocate for a generator-based design approach, where instead of designing one circuit instance, the designer captures their methodology as an executable circuit generator that consists of parameterized procedures which can produce schematic, layout, behavioral model, and verification testbenches from input specifications. With these generators, designers can incorporate fully automated design iteration loops on accurate post-layout simulation data in their design procedure. More importantly, such generators can easily produce many circuit instances for similar applications with different specifications, which promotes design reuse and simplifies complex system design.
This thesis presents BAG, a Python framework that enables the development of process-portable circuit generators. This talk will go over how circuit generators are designed with BAG, and presents various complex circuit generators developed with this framework, including a SerDes generator and a time-interleaved SAR ADC generator. The circuit generators are demonstrated to work in various process nodes, including TSMC 28nm, TSMC 16nm, GF 14nm, GF 45nm RFSOI, and so on.